In recent years, the size and complexity of integrated circuits have increased dramatically. As a result, the computer industry has increasingly moved towards automated design of integrated circuits. In fact, many different systems are currently used to aid an engineer in designing and synthesizing integrated circuits. The circuits designed by these automated systems may not be fully optimized and in fact may produce erroneous circuits. Therefore, the computer generated circuits may require further refining to verify and optimize the design. Circuit verification and circuit optimization require complicated and time consuming analysis. Tools are currently available to aid a circuit designer in verifying and optimizing an integrated circuit.
Heretofore known systems and methods for circuit verification typically use a functional approach. A functional approach uses the functionality of an integrated circuit to either verify or reduce the size and complexity of the circuit. A disadvantage of a functional approach is that it may not be generally applicable to different classes of practical circuits. Hence, a functional approach to circuit verification and optimization may not provide a general framework for an efficient solution. An alternative heretofore known method and system may use a structural approach to verify and optimize an integrated circuit. These structural methods may require less memory than the functional approach. However, these structural methods consume large amounts of processing time.
Various techniques for two-level optimization are well established in the art. However, multi-level circuit optimization is not as well delineated. Even with much recent progress, the size and complexity of today's integrated circuits leave multi-level logic optimization a major challenge in the field of computer aided circuit design. Presently, the most general synthesis techniques for combinational circuits are based on manipulation of boolean functions. Such boolean techniques may be the only techniques which may enable a designer to exploit the full range of possible transformations in a combinational network. These boolean techniques may be able to handle existing circuits of realistic size. However, they may not provide an efficient solution for the ever increasing size of integrated circuits. Structural methods are also currently available for circuit optimization. These techniques suffer from the limitation that they do not provide a general framework that allows a designer to perform all possible transformations in a circuit.
Accordingly, a need has arisen for a fast and efficient method for circuit verification and optimization.